This invention relates to a solid-state image pickup device such as, for example, a MOS type image sensor or a CCD type image sensor and a driving method for the solid-state image pickup device, and more particularly to a configuration of a solid-state image pickup device for achieving reduction of the voltage or expansion of the dynamic range when signal charge produced by a photo-electric conversion element is read out.
FIGS. 11 and 12 show an example of a pixel structure in a conventional CMOS type image sensor, and particularly FIG. 11 is a circuit diagram showing an example of a configuration of a pixel circuit and FIG. 12 is a sectional view showing a structure of some elements of the pixel circuit of FIG. 11.
Here, the CMOS type image sensor is a kind of MOS type image sensor and is called as such because a CMOS-LSI process is applied to form the elements thereof and so forth. However, the CMOS type image sensor need not necessarily be formed fully using a CMOS-LSI process but may partially include some process unique to the image sensor.
The configuration of the pixel circuit is first described with reference to FIG. 11.
According to the pixel circuit shown, each pixel includes a photodiode (PD) 10 and four pixel transistors (Tr) 11, 12, 13 and 14 for transfer, amplification, selection and resetting, respectively.
The photodiode 10 stores electrons produced by photoelectric conversion. The transfer transistor 11 transfers the electrons of the photodiode 10 to a floating diffusion (FD) 15.
The amplification transistor 12 is connected at the gate thereof to the floating diffusion 15 and converts a potential variation of the floating diffusion 15 into an electric signal. The selection transistor 13 selects a pixel from which a signal is to be read out in a unit of a row. When the selection transistor 13 is turned on, the amplification transistor 12 and a constant current source 17 which is connected to a vertical signal line 16 outside the pixel cooperatively form a source follower, and consequently, a voltage which varies in response to the voltage of the floating diffusion 15 is outputted to the vertical signal line 16.
The reset transistor 14 resets the potential of the floating diffusion 15 to a power supply potential Vdd.
FIG. 12 shows a sectional structure of the pixel circuit of FIG. 11 in a region from the photodiode 10 to the floating diffusion 15 through the gate part of the transfer transistor 11.
Referring to FIG. 12, the photodiode 10, a gate portion 11A of the transfer transistor 11 and the floating diffusion 15 are provided in a P-well region 20A formed on a silicon substrate 20, and a gate oxide film or gate insulating film 21 is formed on the silicon substrate 20. An element isolating region 22 of LOCOS is formed at part of the gate oxide film 21.
A transfer gate electrode 11B of the transfer transistor 11 is formed on the gate oxide film 21.
For the photodiode 10, a known embedded photodiode may be used. Where an embedded photodiode is applied, for example, to the photodiode formed in the P-well region 20A, a portion of the silicon substrate 20 in the proximity of an interface of the gate oxide film 21 is formed as a p+ layer or charge separation region 10A and an n layer or charge storage region 10B for storing photoelectrons is formed below the p+ layer 10A to store charge in the deep portion of the silicon substrate 20.
With the embedded photodiode having the configuration just described, since the interface of the n layer 10B is covered with the p+ layer 10A, dark current which may otherwise be generated in the interface of the n layer 10B can be prevented.
Further, if the transfer transistor 11 and the photodiode 10 are designed appropriately, then all photoelectrons of the photodiode 10 can be transferred to the floating diffusion 15. Therefore, the structure of the embedded photodiode 10 described above is used widely in CCD type sensors, and a photodiode having a structure called HAD (Hole Accumulation Diode) structure is provided.
Since the transistors are produced by an ordinary CMOS process, a side wall 11C as a spacer is formed from a silicon oxide film or the like on the transfer gate electrode 11B.
The n layer 10B of the photodiode 10 is formed by ion implantation through self alignment using the transfer gate electrode 11B before the side wall 11C is formed after the transfer gate electrode 11B is formed.
The p+ layer 10A of the photodiode 10 is thereafter formed by ion implantation through self alignment using the side wall 11C after the side wall 11C is formed.
The reason why the n layer 10B and the p+ layer 10A of the photodiode 10 are formed in this manner is that it is intended to assure a very small distance between the p+ layer 10A and the transfer gate electrode 11B with certainty to facilitate transfer of photoelectrons of the photodiode 10.
Meanwhile, the floating diffusion 15 has an LDD structure similarly to an ordinary transistor. According to the LDD structure, an n layer (LDD layer) having a low impurity concentration is formed just below the side wall 11C of the transfer gate portion 11A and an n+ layer (NSD layer) having a high impurity concentration is formed at a distance corresponding to the side wall 11C from the transfer gate portion 11A.
The inventors of the present invention have proposed that, in a solid-state image pickup device having such a structure as described above, a negative voltage of −1 V or the like (here it is called transfer bias voltage) is applied to the transfer gate electrode 11B to suppress dark current (current composed of electrons flowing into the photodiode even if no light is inputted) from the interference below the transfer gate portion 11A.
This is because, where the transfer gate electrode 11B is biased to the negative voltage, a p-type channel 11D is formed in the interface of the gate oxide film 21 below the gate portion 11A and prevents dark current from the interference level similarly to the embedded photodiode 10.
Further, as a method of expanding the dynamic range in a sold-state image pickup device of the type described, a method is known wherein the voltage to the transfer gate or the reset gate is varied during a storage period as disclosed, for example, in Japanese Patent Laid-Open No. Hei 10-248035 (hereinafter referred to as patent document 1).
Incidentally, the pixel configuration described above with reference to FIGS. 11 and 12 has a problem in that the gate voltage necessary to transfer photoelectrons of the photodiode 10 cannot be reduced below a fixed level and therefore it is difficult to reduce the voltage for the CMOS sensor.
In particular, in order for the photodiode 10 to store a required number of electrons, a full depletion voltage of, for example, 1.5 V or more is required. Further, in order to read out all of the electrons of the photodiode 10, when the transfer gate is turned on, a channel having a potential equal to or higher than 1.5 V must be produced at a location deeper than the interference of the gate oxide film 21 so that it may smoothly connect to the n layer of the photodiode 10.
From this reason, there is a problem that, in order to achieve full transfer of the electrons, the gate voltage cannot be set, for example, lower than 2.7 V. This problem is the reverse phase to the problem that, where the same gate voltage is used, it is difficult to transfer photoelectrons of the photodiode to a deeper potential and consequently the number of electrons for saturation is small, that is, it is impossible to assure a sufficient dynamic range. Particularly for a CMOS sensor, a low voltage of 2.5 V or 1.8 V is demanded. However, it is always a subject to be solved how the number of saturation electrons should be increased.
It is to be noted that the subjects described above (reduction of the voltage for the transfer gate and to increase the number of electrons which can be transferred with an equal voltage) are involved similarly as far as a transfer element for receiving a voltage as an input to control the potential is used also where the photodiode is not of the embedded type and where not a photodiode but a photogate is adopted.
The method disclosed in the patent document 1 has the following problems.
First, where the voltage to the transfer gate is varied during a storage period, if a high voltage is inputted to the transfer gate, then when the light amount is great, the photodiode and the floating diffusion are rendered conducting. Therefore, there is a limitation to the operation range.
On the other hand, where the voltage to the reset gate is varied during a storage period, since photoelectrons are stored into a node having a contact such as a floating diffusion, dark current is higher when compared with that where photoelectrons are stored into an embedded photodiode.